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PD - 96190
IRFB4310GPBF
Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits
G
HEXFET(R) Power MOSFET
D
Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free l Halogen-Free
S
VDSS RDS(on) typ. max. ID
100V 5.6m: 7.0m: 130A
S D G
TO-220AB IRFB4310GPBF
Absolute Maximum Ratings
Symbol
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS dV/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw
Max.
130 92 550 300 2.0 20 14 -55 to + 175 300 10lbxin (1.1Nxm) 980 See Fig. 14, 15, 22a, 22b,
Units
A W W/C V V/ns
d
f
C
Avalanche Characteristics
EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy Avalanche CurrentA Repetitive Avalanche Energy
e
g
mJ A mJ
Thermal Resistance
Symbol
RJC RCS RJA Junction-to-Case Case-to-Sink, Flat Greased Surface Junction-to-Ambient
j
Parameter
Typ.
--- 0.50 ---
Max.
0.50 --- 62
Units
C/W
jk
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1
10/15/08
IRFB4310GPBF
Static @ TJ = 25C (unless otherwise specified)
Symbol
V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) IDSS IGSS RG
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Gate Input Resistance
Min. Typ. Max. Units
100 --- --- 2.0 --- --- --- --- --- --- --- 0.064 --- 5.6 7.0 --- 4.0 --- 20 --- 250 --- 200 --- -200 1.4 ---
Conditions
V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 1mAd m VGS = 10V, ID = 75A V VDS = VGS, ID = 250A A VDS = 100V, VGS = 0V VDS = 100V, VGS = 0V, TJ = 125C nA VGS = 20V VGS = -20V f = 1MHz, open drain
g
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
--- 170 46 62 26 110 68 78 7670 540 280 650 720.1 --- 250 --- --- --- --- --- --- --- --- --- --- --- S nC
Conditions
VDS = 50V, ID = 75A ID = 75A VDS = 80V VGS = 10V VDD = 65V ID = 75A RG = 2.6 VGS = 10V VGS = 0V VDS = 50V = 1.0MHz VGS = 0V, VDS = 0V to 80V VGS = 0V, VDS = 0V to 80V
160 --- --- --- --- --- --- --- --- --- --- Effective Output Capacitance (Energy Related)i --- --- Effective Output Capacitance (Time Related)h
ns
g g
pF
i, See Fig.11 h, See Fig. 5
D
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)Ad Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- 130 --- 550 A
Conditions
MOSFET symbol showing the integral reverse
G S
p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 75A, VGS = 0V VR = 85V, --- 45 68 ns TJ = 25C TJ = 125C IF = 75A --- 55 83 di/dt = 100A/s --- 82 120 nC TJ = 25C TJ = 125C --- 120 180 --- 3.3 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
g
g
Notes: Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.35mH RG = 25, IAS = 75A, VGS =10V. Part not recommended for use above this value. ISD 75A, di/dt 550A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For
recommended footprint and soldering techniques refer to application note #AN-994. R is measured at TJ approximately 90C. Coss while VDS is rising from 0 to 80% VDSS .
2
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IRFB4310GPBF
1000
TOP
1000
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
TOP
BOTTOM
VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V
100
10
4.5V
1 0.1 1
60s PULSE WIDTH Tj = 25C
10 10 100 0.1 1
4.5V
60s PULSE WIDTH Tj = 175C
10 100
VDS , Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
Fig 2. Typical Output Characteristics
3.0
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID, Drain-to-Source Current()
2.5
ID = 75A VGS = 10V
100
TJ = 175C
2.0
10
1.5
TJ = 25C VDS = 50V
1.0
60s PULSE WIDTH
1 3.0 4.0 5.0 6.0 7.0 8.0
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
12000 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd 8000
Fig 4. Normalized On-Resistance vs. Temperature
20
VGS, Gate-to-Source Voltage (V)
ID= 75A VDS = 80V VDS= 50V VDS= 20V
10000
16
C, Capacitance (pF)
Ciss
12
6000
8
4000
4
2000
Coss Crss
1 10 100
0
0 0 40 80 120 160 200 240 280 QG Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB4310GPBF
1000.0
10000
ID, Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
TJ = 175C
100.0
OPERATION IN THIS AREA LIMITED BY R DS (on)
1000
100
100sec
10.0
TJ = 25C
1.0
10
1
VGS = 0V
0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Tc = 25C Tj = 175C Single Pulse 1 10
1msec 10msec DC 100 1000
0.1
VSD , Source-to-Drain Voltage (V)
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
V(BR)DSS , Drain-to-Source Breakdown Voltage
140 120
ID, Drain Current (A)
120
Fig 8. Maximum Safe Operating Area
Limited By Package
100 80 60 40 20 0 25 50 75 100 125 150 175 T C , Case Temperature (C)
115
110
105
100 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
Fig 9. Maximum Drain Current vs. Case Temperature
EAS, Single Pulse Avalanche Energy (mJ)
4.0 3.5 3.0
TJ , Junction Temperature (C)
Fig 10. Drain-to-Source Breakdown Voltage
2400
2000
ID 12A 17A BOTTOM 75A
TOP
Energy (J)
2.5 2.0 1.5 1.0 0.5 0.0 0 20 40 60 80 100 120
1600
1200
800
400
0 25 50 75 100 125 150 175
VDS, Drain-to-Source Voltage (V)
Starting TJ, Junction Temperature (C)
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
4
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IRFB4310GPBF
1
D = 0.50
Thermal Response ( ZthJC )
0.1
0.20 0.10 0.05 0.02 0.01
J R1 R1 J 1 2 R2 R2 C 1 2
0.01
Ri (C/W) i (sec) 0.1962 0.00117 0.2542 0.016569
0.001
Ci= i/Ri Ci i/Ri
SINGLE PULSE ( THERMAL RESPONSE )
0.0001 1E-006 1E-005 0.0001 0.001
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.01 0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Duty Cycle = Single Pulse
Avalanche Current (A)
10
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse) 0.01 0.05 0.10
1
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C.
0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
1000
EAR , Avalanche Energy (mJ)
800
TOP Single Pulse BOTTOM 1% Duty Cycle ID = 75A
600
400
200
0 25 50 75 100 125 150 175
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long as neither Tjmax nor Iav (max) is exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13) PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Starting TJ , Junction Temperature (C)
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB4310GPBF
5.0
20
VGS(th) Gate threshold Voltage (V)
4.0
ID = 1.0A ID = 1.0mA ID = 250A
16
3.0
IRRM - (A)
12
8 IF = 30A VR = 85V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
2.0
4
1.0 -75 -50 -25 0 25 50 75 100 125 150 175
0
TJ , Temperature ( C )
dif / dt - (A / s)
Fig 16. Threshold Voltage Vs. Temperature
20
Fig. 17 - Typical Recovery Current vs. dif/dt
500
16
400
QRR - (nC)
IRRM - (A)
12
300
8 IF = 45A VR = 85V TJ = 125C 0 TJ = 25C 100 200 300 400 500 600 700 800 900 1000
200 IF = 30A VR = 85V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
4
100
0
dif / dt - (A / s)
dif / dt - (A / s)
Fig. 18 - Typical Recovery Current vs. dif/dt
500
Fig. 19 - Typical Stored Charge vs. dif/dt
400
QRR - (nC)
300
200 IF = 45A VR = 85V TJ = 125C TJ = 25C 0 100 200 300 400 500 600 700 800 900 1000
100
dif / dt - (A / s)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFB4310GPBF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 22a. Unclamped Inductive Test Circuit
LD VDS
Fig 22b. Unclamped Inductive Waveforms
+
VDD D.U.T VGS Pulse Width < 1s Duty Factor < 0.1%
90%
VDS
10%
VGS
td(on) tr td(off) tf
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id Vds Vgs
L
0
DUT 1K
VCC
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
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Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
7
IRFB4310GPBF
Dimensions are shown in millimeters (inches)
TO-220AB Package Outline
TO-220AB Part Marking Information
@Y6HQG@) UCDTADTA6IADSA7#" BQ7A Ir)AABAAssvAvAhAirA vqvphrAAChytrAAArrA Ir)AAQAAvAhriyAyvrAvv vqvphrAAGrhqAAArrA DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G GPUA8P9@ Q6SUAIVH7@S 96U@A8P9@) 2G6TUA9DBDUAPA 86G@I96SA@6S XX2XPSFAX@@F Y2A68UPSA8P9@
TO-220AB packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.10/2008
8
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